Assembly Hall of Shame
This article explores the "Assembly Hall of Shame," a project dedicated to finding the absolute slowest single-instruction performance on x86 architecture, rather than optimizing for speed. It details strategies for instructions like `fxrstor64` and `nop` to achieve extremely high latency by exploiting memory access patterns and system contention. The goal is to push the boundaries of how long a single CPU instruction can be made to take.
Instruction latency analysis usually focuses on performance optimization —making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
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